The present disclosure relates to a capacitance element and a resonance circuit, and more specifically, to a capacitance element of a multilayer type in which a dielectric layer and an electrode are alternately stacked and a resonance circuit including the same.
In the past, there have been developed various capacitance elements of a multilayer type (hereinafter, referred to as multilayer capacitance element) in each of which a dielectric layer and an internal electrode are alternately stacked. Such capacitance elements are used in various electronic apparatuses. Further, with reduction in size and increase in performance of recent electronic apparatuses, development of smaller, higher-performance multilayer capacitance elements having the above-mentioned structure are being needed.
To serve the need, there have been proposed various kinds of techniques in related art to obtain a smaller, higher-performance multilayer capacitance element (see, domestic republication of PCT international publication WO 05/050679 (hereinafter, referred to as Patent Document 1) and Discussion of Electrode Design in Chip Capacitor for RF Applications, written by Katsuhiko Hayashi, Journal C of The Institute of Electronics, Information and Communication Engineers, Vol. J86-C, No. 8, pp. 927-933, 2003 (hereinafter, referred to as Non-patent Document 1), for example). Patent Document 1 discloses a technique of suppressing a residual stress of the inside or the outer surface of a multilayer capacitance element.
Further, Non-patent Document 1 discloses a technique of providing the multilayer structure of internal electrodes in which the electrodes are prevented from being directly opposed to each other in a stacked direction of dielectric layers of the multilayer capacitance element. In Non-patent Document 1, by using such a multilayer structure of the inner electrodes, variation in capacitance of the multilayer capacitance element is reduced.